This job ad has been posted over 40 days ago...
0

applicants

Full-time Design Verification Engineer

at myfreelancer.org in Texas

Responsibilities
Verification planning, test bench development, failure analysis and resolution, coverage analysis and population, digital/mixed-signal modeling, directed/constraint-random test generation, and flow development.
Qualifications
MSEE/MSCS or a related engineering discipline is required.
5 – 7 years of verification experience preferably in mixed signal products is required.
Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. System Verilog/OVM, UVM, AVM, Vera, etc.) is required.
Solid scripting skills with MatLab, Perl, Unix/Linux shell, TCL, and must be able to write and debug analog behavioral models in Verilog, Verilog-A, and/or Verilog-AMS.
Knowledge of signal processing and Verilog Assertions are also a plus.
Ability to create, evaluate, debug, and improve a verification process is essential for this position.
Ability and experience working in a highly matrixed organizational structure within a diverse culture is preferred.
Proficiency with MS Office (MS Word, MS Excel, MS Outlook, MS PowerPoint, MS Project, etc.) is required.

Please send resume
Reference : Design Verification Engineer jobs


Recent jobs at myfreelancer.org
Full-time Manager, Medical Economics at myfreelancer.org in Delaware 28-03-2018
Full-time Regional Market Manager at myfreelancer.org in California 28-03-2018
Full-time Acoustic Sysyems Engineer at myfreelancer.org in Texas 28-03-2018
Full-time Analog Design Engineer at myfreelancer.org in Texas 28-03-2018
Full-time Design Verification Engineer at myfreelancer.org in Texas 28-03-2018

« Go back to category
Is this job ad fake? Report it!   
Recommend to a friend
Published at 14-03-2018
Viewed: 48 times