This job ad has been posted over 40 days ago...


Full-time Design Verification Engineer

at in Texas

Verification planning, test bench development, failure analysis and resolution, coverage analysis and population, digital/mixed-signal modeling, directed/constraint-random test generation, and flow development.
MSEE/MSCS or a related engineering discipline is required.
5 – 7 years of verification experience preferably in mixed signal products is required.
Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. System Verilog/OVM, UVM, AVM, Vera, etc.) is required.
Solid scripting skills with MatLab, Perl, Unix/Linux shell, TCL, and must be able to write and debug analog behavioral models in Verilog, Verilog-A, and/or Verilog-AMS.
Knowledge of signal processing and Verilog Assertions are also a plus.
Ability to create, evaluate, debug, and improve a verification process is essential for this position.
Ability and experience working in a highly matrixed organizational structure within a diverse culture is preferred.
Proficiency with MS Office (MS Word, MS Excel, MS Outlook, MS PowerPoint, MS Project, etc.) is required.

Please send resume
Reference : Design Verification Engineer jobs

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Published at 14-03-2018
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