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Onsite/Hybrid Role-Physical Design-Power Integrity Engineer at post-active-us-it-job / America Jobs
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Full-time Onsite/Hybrid Role-Physical Design-Power Integrity Engineer

at post-active-us-it-job in Arizona

Onsite/Hybrid Role-Physical Design-Power Integrity Engineer, San
Jose/Phoenix/Austin


Description:
Duration: 12 Months
Location: San Jose/Phoenix/Austin (All open roles required to be onsite/hybrid
on location)

The Work:
Perform comprehensive power analysis in vector and vector-less modes of ASIC
SoC design at different design stages from RTL to gate-level netlist
Develop & own power grid implementation of multi hierarchy low power designs
including power analysis, IR Drop, EM, IR drop based STA in advanced technology
nodes (7nm and below)
Resolve power & power integrity issues related to physical design, identify
potential low power solutions, drive execution and methodology improvements

Here's what you need:
Minimum of 3 years of experience in the following:
o RTL2GDSII design flow on advanced technology nodes (7nm and below)
o Low power implementation and signoff, power gating, multiple voltage rails,
UPF/CPF usage.
o Power integrity analysis at block and top level, including EM, IR & ESD
analysis, power reduction techniques in SOC design
o Power constraints generation and validation, power analysis, interface with
power integrity analysis tools such as thermal analysis.
o TCL, Python and/or Perl programming.
o EDA tools including Redhawk/Voltus , DesignCompiler/Genus,
Primetime/PrimePower/Joules, FusionCompiler/ICC2/Innovus
Bachelor's Degree or equivalent (12 years) work experience (If an,
Associate's Degree with 6 years of work experience)

Bonus points if:
Experience running power analysis in vector and vector-less modes and
achieving optimal QoR on low power designs
Knowledge of static timing analysis, power analysis and concepts, defining
timing and power constraints exceptions, switching activity definitions and
simulation vectors
Experience with power integrity analysis at block level or top level,
including EM, IR & ESD analysis, power reduction techniques in SOC design
Experience with advanced verification techniques such as different booting
verification, end-to-end verification; multiple CPUs verification as part of
the IP is desirable.
Experience in ARM AMBA protocols; AXI4, AHB and APB.
Team player with excellent communication skills and be able to work
independently on the verification efforts for a block/area of the design

Reference : Onsite/Hybrid Role-Physical Design-Power Integrity Engineer jobs


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Published at 12-12-2022
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